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MCET \u2013 ASIC Centre of Excellence was established in the year 2013 with the primary objective of imparting skill set to students in Custom Integrated Circuit on par with present needs of Semiconductor Industry. \u00a0The Memorandum of Understanding (MoU) was signed with M\/s.PicoCircuits Technologies Pvt Ltd, Coimbatore and M\/s. Test and Verification Solutions (A subsidiary of Tessolve semiconductor), Coimbatore and M\/s. Aries Biomedical Technology Pvt Ltd, Coimbatore.<\/p>\n<\/div>\n\t\t<\/div><\/div><\/div><\/div><\/div>

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ASIC Centre of Excellence is passionate in closing the skill and knowledge gaps of today\u2019s Electronics engineers in Custom IC design in the field of Analog, Digital and Mixed signal disciplines and implementation of Signal and Image Processing Architectures.<\/p>\n<\/div>\n<\/div>\n

FACILITIES<\/h4>\n
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The Centre has to its credit the following facilities<\/p>\n
1. State\u2013of\u2013the\u2013art CADENCE EDA suite with 20 user License comprising<\/strong><\/p>\n
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CADANCE VIRTUOSO design environment \u2013For Schematic entry<\/li>\n
CADENCE IES \u2013 For digital and mixed signal verification<\/li>\n
CADENCE ENCOUNTER \u2013 For physical design of digital and mixed signal circuits<\/li>\n
CADENCE ASSURA \u2013 DRC, LVS &Parasitic extraction of analog & mixed signal designs<\/li>\n
CADENCE SPECTRE \u2013 Simulation, analysis & parameter estimation of Analog, Radio<\/li>\n
CADENCE ALLEGRO \u2013PCB Design solution<\/li>\n<\/ul>\n
2. State \u2013of-the-art MENTOR EDA suite with 10 user License comprising.<\/strong><\/p>\n
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MENTOR PYXIS Design Environment \u2013 For schematic entry<\/li>\n
MENTOR QUESTA SIM \u2013 ELDO \u2013 For digital and mixed signal verification<\/li>\n
MENTOR NITRO \u2013 SOC Design<\/li>\n
CALIBRE INROUTE \u2013 For physical design of digital and mixed signal circuits<\/li>\n
MENTOR CALIBRE \u2013 DRC, LVS & Parasitic extraction of analog and mixed signal designs<\/li>\n
MENTOR TESSENT \u2013 Simulation, analysis & parameter estimation of analog, Radio Frequency (RF), And Mixed \u2013Signal Circuits<\/li>\n
MENTOR XPEDITION \u2013 PCB design solution<\/li>\n
TANNER EDA \u2013 For physical design of digital and mixed signal circuits.<\/li>\n<\/ul>\n
3. Server Configuration:<\/strong><\/p>\n
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\u00a0HP DL350_{P\u00a0<\/sub>G8 server, Intel Xeon E5 2609v2 (2.5 Ghz quad core) Processor, 16GB RAM,2\u201d1TB Hard Disk (Extendable).<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<\/div>\n\t\t<\/div><\/div>\t\t\t<\/p>\n<\/div>\n\t\t<\/div><\/div><\/div><\/div><\/div><\/div>\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t
\n\t\t\t\n\t\t\t\t\nTo engage with the Industry on a regular basis to understand their needs and constantly upgrade the hands-on training, Faculty Development Programs(FDPs) and workshops in Custom IC for faculties, industry persons and students.<\/li>\n
To upgrade the infrastructure in VLSI Design relevant to semiconductor industry needs.<\/li>\n
To collaborate with the industries for research programs, projects, student internships and fabrication of Chips<\/li>\n<\/ul>\n\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\n\t\t\t\n\t\t\t\t\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nS. No<\/h4>\n<\/td>\n Name of the Activity<\/strong><\/b><\/td>\n \nBeneficiary<\/h4>\n<\/td>\n No. of\u00a0\u00a0Benefi\nciaries<\/strong><\/b><\/td>\n \nFacilitator\u00a0\/ Expert<\/h5>\n
Consultant \/ Faculty<\/h4>\n
<\/h4>\n<\/td>\n Duration<\/strong><\/b><\/td>\n Date of Activity<\/strong><\/b><\/td>\n Impact<\/strong><\/b><\/td>\n<\/tr>\n
From<\/strong><\/b><\/td>\n \nTo<\/h4>\n
<\/h4>\n<\/td>\n<\/tr>\n
1<\/strong><\/b><\/td>\n Workshop on Analog Design for Medical Devices<\/td>\n Dr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n 139<\/td>\n Shri<\/strong><\/b>\u00a0H.S.Jatana, Group<\/strong><\/b>\u00a0Head \u2013 DPG, SCL, Chandigarh.\n\nShri Ashutosh Yadav,<\/strong><\/b>\u00a0Technical Head, SCL, Chandigarh.<\/td>\n 1 Day<\/td>\n 12.11.22<\/td>\n <\/td>\n Training in Full Custom Design related to Medical Equipments<\/td>\n<\/tr>\n
2<\/strong><\/b><\/td>\n Value Added Course on Full Custom Analog IC Design using Cadence EDA Tool<\/td>\n Dr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n 21<\/td>\n Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate ProfessorDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\nMs.K.Gayathree<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 Days<\/td>\n 28.10.22 & 1.11.22<\/td>\n <\/td>\n Hands-On Training in CMOS Design of NAND and NOR gate<\/td>\n<\/tr>\n
3<\/strong><\/b><\/td>\n Training on Custom digital IC design using Cadence EDA tool<\/td>\n Nachimuthu Polytechnic College, Pollachi<\/td>\n 12<\/td>\n Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n\nMs.K.Gayathree<\/strong><\/b>\n\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 Days<\/td>\n 29.10.22 &\n\n31.10.22<\/td>\n <\/td>\n \n\nTrained in Digital IC Design<\/td>\n<\/tr>\n
4.<\/strong><\/b><\/td>\n Value Added Course on Custom Analog IC Design using Cadence EDA Tool<\/td>\n Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 30<\/td>\n Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n\nMs.S.Dharani<\/strong><\/b>\n\nAssistant Professor\n\nMr.M.Vignesh<\/strong><\/b>\n\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 days<\/td>\n 12.5.22<\/td>\n 13.5.22<\/td>\n \n\nHands-on Training in Physical Design using CADENCE ASSURA<\/td>\n<\/tr>\n
5<\/strong><\/b><\/td>\n Value Added Course on Custom Analog IC Design using Cadence EDA Tool<\/td>\n Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 26<\/td>\n Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 Days<\/td>\n 9.3.21<\/td>\n 10.3.21<\/td>\n Realization of CMOS Gates using Cadence EDA<\/td>\n<\/tr>\n
6<\/strong><\/b><\/td>\n Value Added Course on Custom Analog IC Design using Cadence EDA Tool<\/td>\n Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 30<\/td>\n Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 Days<\/td>\n 5.3.21<\/td>\n 6.3.21<\/td>\n Hands on Session on legging and fingering<\/td>\n<\/tr>\n
7<\/strong><\/b><\/td>\n Value Added Course on Custom Digital IC Design using Cadence EDA Tool<\/td>\n Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 29<\/td>\n Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\nDr.C.Kalamani<\/h4>\nAssistant Professor\n
Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n 2 Days<\/td>\n 12.7.19<\/td>\n 13.7.19<\/td>\n Hands-on Training in timing simulation and parameter estimation using CADENCE encounter<\/td>\n<\/tr>\n
8<\/strong><\/b><\/td>\n Value Added Course on Custom Digital IC Design using Cadence EDA Tool<\/td>\n Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 30<\/td>\n Dr.K.N.Vijeyakumar,<\/strong><\/b>\n\nAssociate Professor\nDr.C.Kalamani<\/h4>\nAssistant Professor\n
Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n 2 Days<\/td>\n 5.3.20<\/td>\n 6.3.20<\/td>\n Training in Clock tree synthesis and Physical design, parameter estimation of digital circuits<\/td>\n<\/tr>\n
9<\/strong><\/b><\/td>\n Implementation of Image Processing Algorithms on FPGA Hardware<\/td>\n Dr. Mahalingam College<\/strong><\/b>\u00a0of Engineering and Technology, Pollachi.\n\n\u00a0Rathinam<\/strong><\/b>\u00a0Technical Campus, Coimbatore.\n\nSSM<\/strong><\/b>\u00a0Institute of Engineering and Technology, Dindigul.\n\nRanganathan<\/strong><\/b>\u00a0Engineering<\/strong><\/b>\u00a0College, Coimbatore.\n\n\u00a0Hindusthan\u00a0Institute\u00a0of Technology, Coimbatore.<\/strong><\/b>\n\nPSNA College<\/strong><\/b>\u00a0of Engineering and Technology, Dindigul.\n\nVivekanandha<\/strong><\/b>\u00a0College<\/strong><\/b>\u00a0of Engineering for Women,\u00a0Tiruchengode.<\/td>\n 28<\/td>\n \nDr.R.Sudhakar<\/strong><\/h4>\nProfessor & Head \/ ECE,\nDr.K.N.Vijeyakumar<\/h4>\nAssociate Professor \/ ECE,\n\nDr.Mahalingam College of Engineering and Technology, Pollachi.\n
Mr.M.Peer\u00a0Mohammed<\/h4>\nResearch Associate,\n\nGovernment College of Technology, Coimbatore.\n\n \n\n <\/td>\n 2 Days<\/td>\n 28.9.2018<\/td>\n 29.9.2018<\/td>\n \n\nHands-on Training on implementation of algorithms for image processing solutions<\/td>\n<\/tr>\n
10<\/strong><\/b><\/td>\n Value Added Course on Custom Analog IC Design using Cadence EDA Tools<\/td>\n Dr. Mahalingam College of Engineering and Technology<\/td>\n 30<\/td>\n Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.C.Kalamani<\/strong><\/b>\n\nAssistant Professor\n\nMs.S.Kalaiselvi<\/strong><\/b>\n\nAssistant Professor\n\nMs.V.Bhuvaneswari<\/strong><\/b>\n\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 Days<\/td>\n 8.2.2019<\/td>\n 9.2.2019<\/td>\n Hands-on Session on design of Ring Oscillator<\/td>\n<\/tr>\n
11<\/strong><\/b><\/td>\n Value Added Course on Custom Analog IC Design using Cadence EDA Tools<\/td>\n Dr. Mahalingam College of Engineering and Technology<\/td>\n 60<\/td>\n \nDr.K.N.Vijeyakumar<\/h4>\n
Associate Professor<\/h4>\n
Dr.C.Kalamani<\/h4>\n
Assistant Professor<\/h4>\n
Ms.S.Kalaiselvi<\/h4>\n
Assistant Professor<\/h4>\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 Days<\/td>\n 28.12.2018<\/td>\n 29.12.2018<\/td>\n CMOS realization of Amplifiers<\/td>\n<\/tr>\n
12<\/strong><\/b><\/td>\n Value Added Course on Custom Analog IC Design using Cadence EDA Tools<\/td>\n Dr. Mahalingam College of Engineering and Technology<\/td>\n 30<\/td>\n Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\nDr.C.Kalamani<\/h4>\n
Assistant Professor<\/h4>\n
Ms.S.Kalaiselvi<\/h4>\n
Assistant Professor<\/h4>\n
Ms.P.Sathyabama<\/h4>\n
Assistant Professor<\/h4>\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 Days<\/td>\n 7.9.2018<\/td>\n 8.9.2018<\/td>\n Design and Analysis of NOR gate with different loads<\/td>\n<\/tr>\n
13<\/strong><\/b><\/td>\n Value Added Course on Custom Analog IC Design using Cadence EDA Tools<\/td>\n Dr. Mahalingam College of Engineering and Technology<\/td>\n 30<\/td>\n Dr.K.N.Vijeyakumar,<\/strong><\/b>\n\nAssociate Professor\nDr.C.Kalamani<\/h4>\n
Assistant Professor<\/h4>\n
Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n 2 Days<\/td>\n 10.8.2018<\/td>\n 18.8.2018<\/td>\n Training on Layout Techniques and design rules<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\n\t\t\t\n\t\t\t\t\t\t\t
\n\t\t\t\n\t\t\t\tPhoto Gallery<\/h3>\n \n \n \n \n \n \n <\/div>\n <\/div>\n <\/div>\n <\/div>\n \n \n \n \n \n \n \n \t\t\t\t\t\n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t\n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t\n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t\n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t\n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t\n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n <\/div>\n <\/div>\n <\/form>\n <\/div>\n <\/div>\n \n <\/div>\n <\/div>\n}

\n S. No<\/h4>\n<\/td>\n	Name of the Activity<\/strong><\/b><\/td>\n	\n Beneficiary<\/h4>\n<\/td>\n	No. of\u00a0\u00a0Benefi\nciaries<\/strong><\/b><\/td>\n	\n Facilitator\u00a0\/ Expert<\/h5>\n Consultant \/ Faculty<\/h4>\n <\/h4>\n<\/td>\n	Duration<\/strong><\/b><\/td>\n	Date of Activity<\/strong><\/b><\/td>\n	Impact<\/strong><\/b><\/td>\n<\/tr>\n
From<\/strong><\/b><\/td>\n	\n To<\/h4>\n <\/h4>\n<\/td>\n<\/tr>\n
1<\/strong><\/b><\/td>\n	Workshop on Analog Design for Medical Devices<\/td>\n	Dr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n	139<\/td>\n	Shri<\/strong><\/b>\u00a0H.S.Jatana, Group<\/strong><\/b>\u00a0Head \u2013 DPG, SCL, Chandigarh.\n\nShri Ashutosh Yadav,<\/strong><\/b>\u00a0Technical Head, SCL, Chandigarh.<\/td>\n	1 Day<\/td>\n	12.11.22<\/td>\n	<\/td>\n	Training in Full Custom Design related to Medical Equipments<\/td>\n<\/tr>\n
2<\/strong><\/b><\/td>\n	Value Added Course on Full Custom Analog IC Design using Cadence EDA Tool<\/td>\n	Dr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n	21<\/td>\n	Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate ProfessorDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n Ms.K.Gayathree<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 Days<\/td>\n	28.10.22 & 1.11.22<\/td>\n	<\/td>\n	Hands-On Training in CMOS Design of NAND and NOR gate<\/td>\n<\/tr>\n
3<\/strong><\/b><\/td>\n	Training on Custom digital IC design using Cadence EDA tool<\/td>\n	Nachimuthu Polytechnic College, Pollachi<\/td>\n	12<\/td>\n	Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n\nMs.K.Gayathree<\/strong><\/b>\n\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 Days<\/td>\n	29.10.22 &\n\n31.10.22<\/td>\n	<\/td>\n	\n\nTrained in Digital IC Design<\/td>\n<\/tr>\n
4.<\/strong><\/b><\/td>\n	Value Added Course on Custom Analog IC Design using Cadence EDA Tool<\/td>\n	Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	30<\/td>\n	Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n\nMs.S.Dharani<\/strong><\/b>\n\nAssistant Professor\n\nMr.M.Vignesh<\/strong><\/b>\n\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 days<\/td>\n	12.5.22<\/td>\n	13.5.22<\/td>\n	\n\nHands-on Training in Physical Design using CADENCE ASSURA<\/td>\n<\/tr>\n
5<\/strong><\/b><\/td>\n	Value Added Course on Custom Analog IC Design using Cadence EDA Tool<\/td>\n	Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	26<\/td>\n	Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 Days<\/td>\n	9.3.21<\/td>\n	10.3.21<\/td>\n	Realization of CMOS Gates using Cadence EDA<\/td>\n<\/tr>\n
6<\/strong><\/b><\/td>\n	Value Added Course on Custom Analog IC Design using Cadence EDA Tool<\/td>\n	Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	30<\/td>\n	Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.N.Saravanakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 Days<\/td>\n	5.3.21<\/td>\n	6.3.21<\/td>\n	Hands on Session on legging and fingering<\/td>\n<\/tr>\n
7<\/strong><\/b><\/td>\n	Value Added Course on Custom Digital IC Design using Cadence EDA Tool<\/td>\n	Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	29<\/td>\n	Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n Dr.C.Kalamani<\/h4>\nAssistant Professor\n Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n	2 Days<\/td>\n	12.7.19<\/td>\n	13.7.19<\/td>\n	Hands-on Training in timing simulation and parameter estimation using CADENCE encounter<\/td>\n<\/tr>\n
8<\/strong><\/b><\/td>\n	Value Added Course on Custom Digital IC Design using Cadence EDA Tool<\/td>\n	Dr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	30<\/td>\n	Dr.K.N.Vijeyakumar,<\/strong><\/b>\n\nAssociate Professor\n Dr.C.Kalamani<\/h4>\nAssistant Professor\n Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n	2 Days<\/td>\n	5.3.20<\/td>\n	6.3.20<\/td>\n	Training in Clock tree synthesis and Physical design, parameter estimation of digital circuits<\/td>\n<\/tr>\n
9<\/strong><\/b><\/td>\n	Implementation of Image Processing Algorithms on FPGA Hardware<\/td>\n	Dr. Mahalingam College<\/strong><\/b>\u00a0of Engineering and Technology, Pollachi.\n\n\u00a0Rathinam<\/strong><\/b>\u00a0Technical Campus, Coimbatore.\n\nSSM<\/strong><\/b>\u00a0Institute of Engineering and Technology, Dindigul.\n\nRanganathan<\/strong><\/b>\u00a0Engineering<\/strong><\/b>\u00a0College, Coimbatore.\n\n\u00a0Hindusthan\u00a0Institute\u00a0of Technology, Coimbatore.<\/strong><\/b>\n\nPSNA College<\/strong><\/b>\u00a0of Engineering and Technology, Dindigul.\n\nVivekanandha<\/strong><\/b>\u00a0College<\/strong><\/b>\u00a0of Engineering for Women,\u00a0Tiruchengode.<\/td>\n	28<\/td>\n	\n Dr.R.Sudhakar<\/strong><\/h4>\nProfessor & Head \/ ECE,\n Dr.K.N.Vijeyakumar<\/h4>\nAssociate Professor \/ ECE,\n\nDr.Mahalingam College of Engineering and Technology, Pollachi.\n Mr.M.Peer\u00a0Mohammed<\/h4>\nResearch Associate,\n\nGovernment College of Technology, Coimbatore.\n\n \n\n <\/td>\n	2 Days<\/td>\n	28.9.2018<\/td>\n	29.9.2018<\/td>\n	\n\nHands-on Training on implementation of algorithms for image processing solutions<\/td>\n<\/tr>\n
10<\/strong><\/b><\/td>\n	Value Added Course on Custom Analog IC Design using Cadence EDA Tools<\/td>\n	Dr. Mahalingam College of Engineering and Technology<\/td>\n	30<\/td>\n	Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n\nDr.C.Kalamani<\/strong><\/b>\n\nAssistant Professor\n\nMs.S.Kalaiselvi<\/strong><\/b>\n\nAssistant Professor\n\nMs.V.Bhuvaneswari<\/strong><\/b>\n\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 Days<\/td>\n	8.2.2019<\/td>\n	9.2.2019<\/td>\n	Hands-on Session on design of Ring Oscillator<\/td>\n<\/tr>\n
11<\/strong><\/b><\/td>\n	Value Added Course on Custom Analog IC Design using Cadence EDA Tools<\/td>\n	Dr. Mahalingam College of Engineering and Technology<\/td>\n	60<\/td>\n	\n Dr.K.N.Vijeyakumar<\/h4>\n Associate Professor<\/h4>\n Dr.C.Kalamani<\/h4>\n Assistant Professor<\/h4>\n Ms.S.Kalaiselvi<\/h4>\n Assistant Professor<\/h4>\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 Days<\/td>\n	28.12.2018<\/td>\n	29.12.2018<\/td>\n	CMOS realization of Amplifiers<\/td>\n<\/tr>\n
12<\/strong><\/b><\/td>\n	Value Added Course on Custom Analog IC Design using Cadence EDA Tools<\/td>\n	Dr. Mahalingam College of Engineering and Technology<\/td>\n	30<\/td>\n	Dr.K.N.Vijeyakumar<\/strong><\/b>\n\nAssociate Professor\n Dr.C.Kalamani<\/h4>\n Assistant Professor<\/h4>\n Ms.S.Kalaiselvi<\/h4>\n Assistant Professor<\/h4>\n Ms.P.Sathyabama<\/h4>\n Assistant Professor<\/h4>\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 Days<\/td>\n	7.9.2018<\/td>\n	8.9.2018<\/td>\n	Design and Analysis of NOR gate with different loads<\/td>\n<\/tr>\n
13<\/strong><\/b><\/td>\n	Value Added Course on Custom Analog IC Design using Cadence EDA Tools<\/td>\n	Dr. Mahalingam College of Engineering and Technology<\/td>\n	30<\/td>\n	Dr.K.N.Vijeyakumar,<\/strong><\/b>\n\nAssociate Professor\n Dr.C.Kalamani<\/h4>\n Assistant Professor<\/h4>\n Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n	2 Days<\/td>\n	10.8.2018<\/td>\n	18.8.2018<\/td>\n	Training on Layout Techniques and design rules<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t \n\t\t\t\n\t\t\t\t \t\t\t \n\t\t\t\n\t\t\t\t Photo Gallery<\/h3>\n \n \n \n \n \n \n <\/div>\n <\/div>\n <\/div>\n <\/div>\n \n \n \n \n \n \n \n \t\t\t\t\t $\"IMAGE_3-600-x-600\"\n\t\t\t\t\t\t\t\t\t\t$ \n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t $\"IMAGE_4-600-x-600\"\n\t\t\t\t\t\t\t\t\t\t$ \n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t $\"IMAGE_2-600-x-600\"\n\t\t\t\t\t\t\t\t\t\t$ \n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t $\"IMAGE_6-600-x-600\"\n\t\t\t\t\t\t\t\t\t\t$ \n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t $\"IMAGE_1-600-x-600\"\n\t\t\t\t\t\t\t\t\t\t$ \n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n \n \n \n \n \t\t\t\t\t $\"IMAGE_5-600-x-600\"\n\t\t\t\t\t\t\t\t\t\t$ \n \n \t\t\t\t <\/div>\n <\/div>\n <\/div>\n <\/a>\n <\/div>\n <\/div>\n <\/div>\n <\/form>\n <\/div>\n <\/div>\n \n <\/div>\n <\/div>\n

S. No<\/h4>\n<\/td>\n

Beneficiary<\/h4>\n<\/td>\n

Facilitator\u00a0\/ Expert<\/h5>\n

Consultant \/ Faculty<\/h4>\n

<\/h4>\n<\/td>\n

To<\/h4>\n

<\/h4>\n<\/td>\n<\/tr>\n

Ms.K.Gayathree<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n

Dr.C.Kalamani<\/h4>\nAssistant Professor\n

Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n

Dr.C.Kalamani<\/h4>\nAssistant Professor\n

Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi.<\/td>\n

Dr.R.Sudhakar<\/strong><\/h4>\nProfessor & Head \/ ECE,\nDr.K.N.Vijeyakumar<\/h4>\nAssociate Professor \/ ECE,\n\nDr.Mahalingam College of Engineering and Technology, Pollachi.\nMr.M.Peer\u00a0Mohammed<\/h4>\nResearch Associate,\n\nGovernment College of Technology, Coimbatore.\n\n \n\n <\/td>\n

Dr.K.N.Vijeyakumar<\/h4>\nAssociate Professor \/ ECE,\n\nDr.Mahalingam College of Engineering and Technology, Pollachi.\n

Mr.M.Peer\u00a0Mohammed<\/h4>\nResearch Associate,\n\nGovernment College of Technology, Coimbatore.\n\n \n\n <\/td>\n

Dr.K.N.Vijeyakumar<\/h4>\n

Associate Professor<\/h4>\n

Dr.C.Kalamani<\/h4>\n

Assistant Professor<\/h4>\n

Ms.S.Kalaiselvi<\/h4>\n

Assistant Professor<\/h4>\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n

Dr.C.Kalamani<\/h4>\n

Assistant Professor<\/h4>\n

Ms.S.Kalaiselvi<\/h4>\n

Assistant Professor<\/h4>\n

Ms.P.Sathyabama<\/h4>\n

Assistant Professor<\/h4>\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n

Dr.C.Kalamani<\/h4>\n

Assistant Professor<\/h4>\n

Ms.S.Kalaiselvi<\/h4>\nAssistant Professor\n\nDr. Mahalingam College of Engineering and Technology, Pollachi<\/td>\n

Photo Gallery<\/h3>\n \n \n \n \n \n \n <\/div>\n <\/div>\n <\/div>\n <\/div>\n \n \n \n \n \n \n \n \t\t\t\t\t\n

Dr.R.Sudhakar<\/strong><\/h4>\nProfessor & Head \/ ECE,\n
Dr.K.N.Vijeyakumar<\/h4>\nAssociate Professor \/ ECE,\n\nDr.Mahalingam College of Engineering and Technology, Pollachi.\n
Mr.M.Peer\u00a0Mohammed<\/h4>\nResearch Associate,\n\nGovernment College of Technology, Coimbatore.\n\n \n\n <\/td>\n